1. Field of the Invention
The present invention relates to circuits and methods for generating a reference voltage. More particularly, the present invention relates to circuits and methods for generating a reference voltage by using both an external reference voltage generating circuit and an internal reference voltage generating circuit.
2. Description of the Related Art
In general, “logic level” refers to signals that are at a low voltage when in the logic “low” or “false” state, and at a specified higher voltage when in the logic “high” or “true” state. Generally, a predetermined reference voltage is used to determine whether a received digital data signal is in a logic “high” state or logic “low” state in order to perform data transmission between chips in computers. The reference voltage may have an average value between a voltage level corresponding to a logic “high” state and a voltage level corresponding to a logic “low” state so that the reference voltage can be compared to an input digital data signal.
Generally, the voltage level of the input data signal is compared to the reference voltage by an input buffer of a receiver, which may include a differential amplifier as a comparator and the comparison result is transmitted to an internal logic of the receiver.
FIG. 1 is a block diagram illustrating a reference voltage for use in the data transmission. Referring to FIG. 1, a reference voltage Vref is applied to an input buffer 110 of a chip 100 and compared to a voltage level of a data input signal Vin received through a data receiving pad 130. When the voltage level of the data input signal Vin is higher than the voltage level of the reference voltage Vref, an output signal Vout having a logic “high” level is outputted to the internal logic of the chip 100. When the voltage level of the data input signal Vin is lower than the voltage level of the reference voltage Vref, the output signal Vout having a logic “low” level is outputted to the internal logic of the chip 100.
Therefore, the stability of the reference voltage Vref greatly affects data transmission accuracy. If the reference voltage Vref varies, the setup time and hold time of an input signal, which become shorter as the data rate increases, may be different from the values designated in the design process of a chip.
Thus, the reference voltage Vref, which needs to be kept stable, may fluctuate for various reasons. First, signal interference caused by parasitic capacitance of a MOS transistor of the input buffer that receives the reference voltage may affect a voltage level of the reference voltage. Particularly, a magnitude of the signal interference may increase as the data transmission rate increases. In addition, the reference voltage may be affected by noise on the power supply voltage, variations in a process of each chip, and variations in internal temperature, etc.
Various interface standards specify interfaces in data transmission between a memory chip and a memory controller. There are standards which specify either a method of receiving an external reference voltage through a pad or a method of generating an internal reference voltage.
FIGS. 2A and 2B are schematic views illustrating a conventional method of generating a reference voltage. Referring to FIG. 2A, a reference voltage VREFint is generated based on an internal power supply voltage 201 of a chip. Particularly, the reference voltage VREFint is generated by dividing the internal power supply voltage 201 using a pull-up resistor 203 and a pull-down resistor 204.
Referring to FIG. 2B, a reference voltage VREFext is generated outside the chip, based on an external power supply voltage 211 of the chip. Similarly to FIG. 2A, the reference voltage VREFext is generated by dividing the external power supply voltage 211 using a pull-up resistor 213 and a pull-down resistor 214. The reference voltage VREFext may be provided to the chip through a pad 215.
Each method of generating the reference voltage VREFint or VREFext as described above with reference to FIGS. 2A and 2B has its advantages and disadvantages.
First, in the method of generating the reference voltage VREFext outside the chip, the reference voltage VREFext having a fixed voltage level is provided to the chip without any compensation for variations in process, temperature, etc. However, using the reference voltage VREFext may be advantageous, in that the reference voltage VREFext is not interfered with by the noise on the internal power supply voltage of the chip.
In the method of generating the reference voltage VREFint, the reference voltage VREFint may be interfered with by the noise on the internal power supply voltage of the chip, in contrast to with the reference voltage VREFext which is not interfered with by the noise on the internal power supply voltage of the chip. When various circuit components are integrated in one chip to implement a system, especially for a semiconductor device, a number of transistors may be integrated on the chip to increase an integration level of the semiconductor device. In such cases, as the numerous transistors in the semiconductor device are repeatedly turned on and off, the amount of variation in current through the transistors is increased, causing the power supply voltage to be unstable. The instability of the power supply voltage may have an influence on the reference voltage. However, the method of generating the reference voltage VREFint may be advantageous in that the reference voltage VREFint may compensate for the variations in process, temperature, etc.
Thus, because of the aforementioned trade-off relationship between the two methods, attaining the stability of the reference voltage by using only one of the two methods is difficult.
A conventional automatic mode selection circuit, which is disclosed in U.S. Pat. No. 5,818,783, includes external reference voltage delivery means for delivering an external high-speed input/output reference voltage in a high-speed input/output interface mode and internal reference voltage generation means for generating an internal transistor-transistor logic reference voltage in a low-voltage transistor-transistor logic (LVTTL) mode. The automatic mode selection circuit according to U.S. Pat. No. 5,818,783 automatically selects one of the low-voltage transistor-transistor logic (LVTTL) mode and the high-speed input/output interface mode in a semiconductor memory device. The automatic mode selection circuit according to U.S. Pat. No. 5,818,783 is directed to reducing an occupied area on a chip and operation speed improvement, but not directed to improving the stability of the reference voltage.
In addition, a conventional circuit for generating a reference voltage is disclosed in Korean Patent No. 0267088, which includes means for generating an internal reference voltage, a pad to which an external reference voltage is applied, means for selecting one of the internal reference voltage and an external reference voltage and switching means for outputting a selected reference voltage. Korean Patent No. 0267088 does not discuss methods to improve the stability of the reference voltage.